New useful additions!

In my previous post I mentioned the mainframe instrument I purchased.  I had another run of luck on eBay and was able to purchase a few more pieces.  I was able to obtain at 2 channel scope and a 102 channel logic analyzer card.

The oscilloscope card has good specifications: 2 channels, each with a 2 GS/sec 8 bit analog to digital converter. Each channel is capable of 500 MHz Bandwidth.  The logic analyzer card is capable of 500 MHz timing and 100 MHz state analysis with 102 channels.  The new configuration is shown in the picture below.

Current Configuration

The initial oscilloscope card tests were done using my function generator hooked up to both channels with the same signal function output.  In the screenshot below, you can see the 3 MHz sin waves shown on both channels.

Function Generator Scope Trace

I decided it to test out the new cards using an FPGA development board I have laying around.  I set up the design logic to output 16 signals for logic analysis as well as clock outputs for the scope channels.  A picture of the board setup to test the instrument cards is below.

Test Setup

I hooked up one of the flying lead pods up to the logic analyzer cable, then to the pins on the FPGA development board.  The oscilloscope probes and logic analyzer clock input line are connected to clock output pins as well.   I wrote some simple VHDL to synthesize some signals to test the logic analyzer and to output the clock signals.  The screenshot from the oscilloscope below shows that the clock output is 50 MHz.

FPGA Scope Trace

The clock signal isn't super clean and you would want to use a Schmitt trigger to clean that up before using it to drive something.  At least we can verify that the 50 MHz clock going into the FPGA can be forwarded out of the FPGA.  

The logic trace is very busy as you can see below.  The labels on the left side designate which pin on the FPGA development board the leads are connected to.

FPGA Logic Trace

The next thing for me to tackle is to figure out how to setup an inter-module trigger and run that as a group.  I know this will be useful in the future with some up coming projects.  Have fun everyone, see you next time.