library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity TestProject is
Port (
Clk_In : in std_logic; -- Clock in from board (50 Mhz)
led_1 : out std_logic; -- Labeled D2 on board
led_2 : out std_logic; -- Labeled D4 on board
led_3 : out std_logic -- Labeled D5 on board
);
end TestProject;
architecture RealTimeLogic of TestProject is
constant slow_count : natural := 48000000;
constant fast_count : natural := 12000000;
signal Reset : std_logic;
begin
Reset <= '0'; -- Clear Reset.
alternating_led_sequence : process(Clk_In,Reset)
variable alternating_led_counter: natural range 0 to slow_count;
begin
if Reset = '1' then
alternating_led_counter := 0;
led_1 <= '1';
led_2 <= '1';
elsif rising_edge(Clk_In) then
-- Handle the Oscillating Led sequence.
if alternating_led_counter < slow_count/2 then
alternating_led_counter := alternating_led_counter + 1;
led_1 <= '1';
led_2 <= '0';
elsif alternating_led_counter < slow_count then
led_1 <= '0';
led_2 <= '1';
alternating_led_counter := alternating_led_counter + 1;
else
led_1 <= '1';
led_2 <= '0';
alternating_led_counter := 0;
end if;
end if;
end process alternating_led_sequence;
blinking_led_sequence : process(Clk_In,Reset)
variable blink_counter : natural range 0 to fast_count;
begin
if Reset = '1' then
blink_counter := 0;
led_3 <= '1';
elsif rising_edge(Clk_In) then
-- Handle the fast blinking Led Sequence
if blink_counter < fast_count/4 then
blink_counter := blink_counter + 1;
led_3 <= '1';
elsif blink_counter < fast_count then
led_3 <= '0';
blink_counter := blink_counter + 1;
else
led_3 <= '1';
blink_counter := 0;
end if;
end if;
end process blinking_led_sequence;
end RealTimeLogic;
